Memory with minimized redundancy access delay

Details Memory with minimized redundancy access delay Memory with minimized redundancy access delay

1993-08-24

1995-01-10

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

36518907, 36523006, G11C 700, G11C 800

Patent

active

053813707

ABSTRACT:
A memory is described that includes a main memory array having a plurality of main memory locations and a redundant memory array having a plurality of redundant memory locations. A main decoding circuit is coupled to the main memory array for decoding an address received from an external circuit to access a selected one of the plurality of main memory locations. A storage circuit is provided for pre-storing the address of the selected one of the plurality of main memory locations when the selected one of the plurality of main memory locations is defective. A redundant comparison circuit is coupled to the redundant memory array and the storage circuit for comparing the external address with the address stored in the storage circuit in order to access a selected one of the plurality of redundant memory locations. A static decoding circuit is coupled to the storage circuit and the main select circuit for decoding the address received from the storage circuit and for disabling the main select circuit from accessing the selected one of the plurality of main memory locations such that when the redundant comparison circuit accesses the selected one of the plurality of redundant memory locations, the main select circuit has already been disabled from accessing the selected one of the plurality of main memory locations.

REFERENCES:
patent: 4807191 (1989-02-01), Flannagan
patent: 5031142 (1991-07-01), Castro
patent: 5083294 (1992-01-01), Okajima
patent: 5233559 (1993-08-01), Brennan, Jr.
patent: 5267205 (1993-11-01), Hamada
-B. F. Fitzgerald and D. W. Kemerer, "Memory System with High-Performance Word Redundancy," IBM Technical Disclosure Bulletin, vol. 19, No. 5, pp. 1638-1639 (Oct. 1976).

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