Semiconductor memory device and an operating method of the same

Details Semiconductor memory device and an operating method of the same Semiconductor memory device and an operating method of the same

1993-03-24

1995-01-10

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

36518903, 365221, 36523001, 36523004, 36523009, 365239, G11C 700, G11C 800

Patent

active

053813677

ABSTRACT:
First and second input/output line groups are provided. A plurality of first bit line groups are connected to the first input/output line group through corresponding column selecting circuits, respectively. A plurality of second bit line groups are connected to the second input/output line group through corresponding column selecting circuits, respectively. A column decoder activates one of the column selecting circuits corresponding to the first bit line group and one of the column selecting circuits corresponding to the second bit line group at the same time or with a predetermined time difference.

REFERENCES:
patent: 5150327 (1992-09-01), Matsushima et al.
patent: 5229971 (1993-07-01), Kiryu et al.
patent: 5299161 (1994-03-01), Choi et al.
patent: 5313423 (1994-05-01), Sato et al.
Masao Taguchi et al, A 40ns 64Mb DRAM with Current-Sensing Data-Bus Amplifier, IEEE International Solid-State Circuits Conference, 1991, pp. 112-113.

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