Processor controlled link resiliency circuit for serial storage

Details Processor controlled link resiliency circuit for serial storage Processor controlled link resiliency circuit for serial storage

1997-04-11

1999-08-03

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

G06F 1100

Patent

active

059319585

ABSTRACT:
A serial storage architecture (SSA) storage subsystem includes a backplane, first and second storage devices, each equipped with a link resiliency circuit, connected to the backplane, an SSA initiator and a series of SSA targets, which include a backplane of the storage pod and the first and second storage devices, serially connected to the SSA initiator. Control and status registers are coupled to the link resiliency circuits. The control register transmits control signals, such as time required for the link resiliency circuits to heal line faults, to the link resiliency circuits in response to commands issued by the SSA initiator. The status register is polled by a controller to the presence of line faults detected by the link resiliency circuits. If so, the detected line faults are reported to the SSA initiator.

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