Branch instruction handling in a self-timed marking system

Details Branch instruction handling in a self-timed marking system Branch instruction handling in a self-timed marking system

1997-12-23

1999-08-03

Treat, William M.

Electrical computers and digital processing systems: processing

Processing control

Branching

712204, 712210, 712212, 712213, 712206, G06F 930

Patent

active

059319445

ABSTRACT:
An instruction execution pipeline in a computer system having variable-length instructions uses branch prediction to perform self-timed marking of instructions prior to decoding. Branch handling logic is provided in an instruction marking circuit to directly mark a target instruction of a predicted branch as the next instruction to be decoded. Additionally, a branch target FIFO may be used to store information about the location of the target instruction in the instruction stream.

REFERENCES:
patent: 5488710 (1996-01-01), Sato et al.
patent: 5535347 (1996-07-01), Grochowski et al.
patent: 5752069 (1998-05-01), Roberts et al.
patent: 5758116 (1998-05-01), Lee et al.
patent: 5852727 (1998-12-01), Narayan et al.
patent: 5870599 (1999-02-01), Hinton et al.

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