Method and apparatus for management of peripheral devices couple

Details Method and apparatus for management of peripheral devices couple Method and apparatus for management of peripheral devices couple

1996-06-28

1999-12-07

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 34, 714 56, 710 17, 710 22, 710110, 710101, G06F 11273

Patent

active

060000430

ABSTRACT:
A method and apparatus for operating a peripheral system having one or more peripheral devices coupled to at least one bus is described. When a bus master initiates a transaction with a peripheral device that ends in an abort condition (such as a Master Abort condition in a PCI architecture), the bus master generates an interrupt (such as the System Management Interrupt) to a central processing unit (CPU). When the interrupt is received, the CPU then attempts to determine the cause of the abort condition. For example, if the peripheral device is operating in a low power consumption mode, the CPU attempts to power up the device so that a retry of the transaction will be successful. Since the peripheral devices can be kept in a low power consumption mode until accessed by a bus master, the power consumption for the computer system is greatly reduced.

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