Semiconductor memory device with folded bit line structure suita

Details Semiconductor memory device with folded bit line structure suita Semiconductor memory device with folded bit line structure suita

1989-06-09

1990-05-01

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

365 51, 36518901, G11C 1300, G11C 1140

Patent

active

049224603

ABSTRACT:
Provided is a memory cell array structure in a DRAM capable of easily reducing the area occupied by a memory cell array while retaining advantages of a folded bit line structure. The memory cell array comprises a plurality of memory cell array blocks each divided into two subblocks. Each of the subblocks has a structure in which the first bit lines each having a predetermined number of memory cells connected, second bit lines which are pass bit lines each comprising only an interconnection layer and third bit lines having a predetermined number of memory cells connected are repeatedly arranged in this order. In addition, the second bit lines in one sub-array block are connected to the third bit lines in the other sub-array block, and the third bit lines in one sub-array block are connected to the second bit lines in the other sub-array block. Furthermore, each of the sub-array blocks comprises sense amplifiers for differently amplifying signals on the first bit lines and the second bit lines in each of the sub-array blocks.

REFERENCES:
patent: 3518640 (1970-06-01), Cassidy
patent: 3646531 (1972-02-01), Marahashi
patent: 3681767 (1972-08-01), Moore
patent: 3942164 (1976-03-01), Dunn
patent: 4675845 (1987-06-01), Itoh et al.
patent: 4733374 (1988-03-01), Furuyama et al.
patent: 4739497 (1988-04-01), Itoh et al.
patent: 4739500 (1988-04-01), Miyamoto et al.

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