Semiconductor memory device having a plurality of selectively ac

Details Semiconductor memory device having a plurality of selectively ac Semiconductor memory device having a plurality of selectively ac

1991-07-16

1993-08-24

Grimm, Siegfried H.

Static information storage and retrieval

Read/write circuit

Including signal clamping

36518909, 365204, G11C 700

Patent

active

052395081

ABSTRACT:
A semiconductor memory device comprises a memory cell array including a plurality of memory cells, a plurality of word lines and bit lines connected to the memory cells, a data bus for carrying data to be written in and/or read out from a selected memory cell, an addressing circuit for selecting one of the word lines and bit lines, an input buffer for outputting the electric signal indicative of the data to be written on the data bus, a current-mirror amplifier connected to the data bus for amplifying the electric signals that are read out from the memory cell on the data bus, and a limiter circuit connected to the data bus for limiting a voltage swing of the electric signals on the data bus. The limiter circuit maintains the data bus at a predetermined voltage level and limits the voltage level of the electric signals supplied to the current-mirror amplifier, wherein the limiter circuit changes the predetermined voltage level in response to a voltage level of a supply voltage that powers the current-mirror amplifier.

REFERENCES:
patent: 4829479 (1989-05-01), Mitsumoto et al.
patent: 5091886 (1992-02-01), Miyawaki et al.

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