Semiconductor memory device and method of checking same for defe

Details Semiconductor memory device and method of checking same for defe Semiconductor memory device and method of checking same for defe

1998-04-13

1999-12-07

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 36523006, G11C 2900

Patent

active

059994649

ABSTRACT:
A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

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