Low power combinational logic circuit

Details Low power combinational logic circuit Low power combinational logic circuit

1996-06-11

1998-10-06

Santamauro, Jon

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 68, 326 81, H03K 190175

Patent

active

058182560

ABSTRACT:
The power consumption by a combinational logic circuit having primary input and output terminals is reduced. The constituent gates of the combinational logic are clustered in terms of the operating voltage levels thereof. First, the gates driven with the highest operating voltage are clustered just adjacent to the primary input terminals. Next, the gates driven with the next higher voltage are clustered adjacent to the primary input terminals only through the gates driven with the highest voltage, followed by repetition of the same clustering procedure in the order of the operating voltage level. Finally, the gates driven with the lowest operating voltage are clustered just adjacent to the primary output terminals.

REFERENCES:
patent: 4477740 (1984-10-01), Takeda
patent: 4853560 (1989-08-01), Iwamura et al.
patent: 4977339 (1990-12-01), Denda
patent: 5067003 (1991-11-01), Okamura
patent: 5084637 (1992-01-01), Gregor
patent: 5126597 (1992-06-01), Usami et al.
patent: 5313079 (1994-05-01), Brasen et al.
patent: 5352942 (1994-10-01), Tanaka et al.
patent: 5594368 (1997-01-01), Usami

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