Self-aligned T-shaped process for deep submicron Si MOSFET's fab

Details Self-aligned T-shaped process for deep submicron Si MOSFET's fab Self-aligned T-shaped process for deep submicron Si MOSFET's fab

1998-07-30

1999-12-07

Chaudhuri, Olik

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438182, 438183, H01L 21336

Patent

active

059982853

ABSTRACT:
A process is disclosed for the fabrication of a MOS device with a T-shaped gate electrode, in which a selective CVD technique has been utilized to simplify the T-shaped gate process. After the formation of the gate oxide layer, no reactive ion etching step is applied, and that avoids the plasma charging damage to the gate oxide. The lightly-doped-drain structure and heavily-doped drain and source areas are formed in a self-aligned manner during the T-shaped gate process. The present invention provides a high yield rate and cost-saving in the T-shaped gate process for MOS devices.

REFERENCES:
patent: 5858843 (1999-01-01), Doyle et al.
patent: 5891783 (1999-04-01), Liu et al.
patent: 5918130 (1999-06-01), Hause et al.

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