System-on-chip layout compilation

Details System-on-chip layout compilation System-on-chip layout compilation

1997-03-13

1999-03-16

Teska, Kevin J.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

058838147

ABSTRACT:
A layout compiler compiles from hardware description language (HDL) and schematic description of a design, which consists of dynamic random access memory (DRAM) components and logic components, to the layout of an integrated logic and DRAM system on a single integrated chip. The layout compiler creates the physical structure (floor-plan) of integrated logic/DRAM chips and generates on-chip interconnections between the DRAM components and logic components. By integrating logic and DRAM memory onto the same chip, the performance gap which is the difference between the logic processor's data processing rate and the DRAM memory's data access rate can be minimized. Further, the bandwidth between the logic processor and the DRAM memory can be increased significantly. The layout methods eliminate the off-chip drivers and heavy capacitive loads presented in the off-chip interconnections. Low power dissipation is a direct result of integrated logic/DRAM chip in high frequency operations. This method enables the optimization of the on-chip metal interconnections between the logic components and the DRAM components in a way to achieve higher system bandwidth and system performance, lower power dissipation and packaging cost.

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Akira Yamazaki, et al., "A Cache DRAM for Graphic Application", Oct. 1993, Technical Report of IEICE, pp. 9-14.

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