Nonvolatile semiconductor memory device with a bias circuit

Details Nonvolatile semiconductor memory device with a bias circuit Nonvolatile semiconductor memory device with a bias circuit

1988-08-23

1989-06-27

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, 365208, G11C 1140

Patent

active

048435945

ABSTRACT:
A nonvolatile semiconductor memory device is disclosed comprising a bit line connected to the drain of a memory cell transistor forming a nonvolatile memory cell, a first p-channel MOS transistor, the drain and gate of the first transistor being connected to a node, and the source of the first transistor being connected to a power source potential, second and third n-channel MOS transistors connected in series between the node and a reference potential, the drain and gate of the second transistor being interconnected, and the drain and gate of the third transistor being interconnected, and a fourth n-channel MOS transistor for controlling charging of the bit line, one terminal of the drain-source path of the fourth transistor being connected to the power source potential and the other terminal being connected to the bit line, and the gate of the fourth transistor being connected to the node.

REFERENCES:
patent: 4223394 (1980-09-01), Pathak et al.
patent: 4694429 (1987-09-01), Tanaka et al.

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