Semiconductor memory device including a memory cell region of si

Details Semiconductor memory device including a memory cell region of si Semiconductor memory device including a memory cell region of si

1996-02-14

1998-10-06

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257369, 257371, 257380, 257393, 365154, 365174, H01L 29788

Patent

active

058180800

ABSTRACT:
A semiconductor memory device is provided that can have the memory cell size reduced and electrical imbalance eliminated. This semiconductor memory device has gate electrodes of a driver transistor and a load transistor formed of a first polysilicon layer, and a word line also serving as a gate electrode of an access transistor formed of a different layer of a second polysilicon layer. Therefore, the gate electrodes of the driver transistor and the load transistor can be overlapped with each other in a planar manner with the word line, resulting in reduction in the planar area of the memory cell. In a cell current path, a contact portion other than a bit line contact and a GND contact is not provided. Therefore, electrical imbalance in memory cells is prevented.

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Fumitomo Matsuoka et al, "High-Denisty Full-CMOS SRAM Cell Technology with a Deep Sub-Micron Spacing between nMOS and pMOSFET," IEICE Trans. Election., vol. E77-C, No. 8, Aug. 1994, pp. 1385-1394.

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