Semiconductor device having at least two field effect transistor

Details Semiconductor device having at least two field effect transistor Semiconductor device having at least two field effect transistor

1991-03-26

1993-05-18

Wojciechowicz, Edward J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

437 29, 437 34, 437 35, 437 41, 257328, 257346, H01L 2702, H01L 21265

Patent

active

052125424

ABSTRACT:
A complementary field effect transistor with an N channel MOSFET and a P channel MOSFET formed on the same substrate is disclosed. On the P type main surface of the semiconductor substrate, an N channel MOSFET is formed comprising a gate electrode and a pair of impurity regions which becomes a pair of source/drain regions. Each impurity region of the N channel MOSFET comprises an impurity region of relatively low concentration formed so as to extend to beneath the above mentioned gate electrode, and an impurity region having a concentration higher than that of said impurity region having low concentration formed in a position at a distance from said gate electrode joining the impurity region of low concentration. The length of the portion located beneath the above mentioned gate electrode in the surface portion of the impurity region of low concentration is not less than 0.1 .mu.m in the direction identical to the direction of the channel length. This complementary field effect transistor has both reliability and high speed in the N channel MOSFET, and without punch-through in the P channel MOSFET, even though the devices become more minute.

REFERENCES:
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patent: 4937645 (1990-06-01), Ootsuka et al.
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Vyas et al-IEEE Transactions on Electron Devices, vol. ED-32, No. 5, May, 1985, pp. 926-930.
Pfiester et al.-IEEE Transactions on Electron Devices, vol. 36, No. 11, Nov. 1989, pp. 2422-2432.
Tsang, et al., "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", IEEE Transactions of Electron Devices, vol. ED-29, No. 4 (Apr. 1982), pp. 590-596.
Inuishi et al, 1988 Symposium on VLSI Technology, Digest of Technical Papers, pp. 33-34 (May 22, 1988, Kyoto, Japan).

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