MOSFET device having denuded zones for forming alignment marks

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257274, 257647, 257648, 437 10, 437 34, H01L 2980, H01L 2976, H01L 2358

Patent

active

056939760

ABSTRACT:
A process for fabricating MOSFET devices, in which a denuded zone in silicon has been created during the normal process sequence, has been developed. In order to avoid the formation of deleterious oxygen precipitates, prior to the creation of the denuded zone, low temperature processing had to be used. Low temperature insulator depositions were used for the alignment mark formation, as well as for the fill for the field oxide regions. Subsequently, high temperature well formation activation anneals, resulted in the creation of the denuded zone, and thus removed the low temperature restriction for the remaining processing steps.

REFERENCES:
patent: 4661166 (1987-04-01), Hirao
patent: 4764248 (1988-08-01), Bhattacherjee et al.
patent: 5107321 (1992-04-01), Ilderem et al.

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