Semiconductor static RAM having thin film transistor gate connec

Details Semiconductor static RAM having thin film transistor gate connec Semiconductor static RAM having thin film transistor gate connec

1993-01-15

1994-07-05

Limanek, Robert

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257 67, 257393, 257903, H01L 2702

Patent

active

053270037

ABSTRACT:
A semiconductor memory device includes a semiconductor substrate, a memory cell provided on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, where each of the first and second transfer transistors, the first and second driver transistors and the first and second thin film transistor loads have a source, a drain and a gate electrode, and a connecting region in which the drain of the second thin film transistor load, the gate electrode of the first thin film transistor load and the gate electrode of the first driver transistor are connected. The gate electrode of the first driver transistor, the gate electrode of the first thin film transistor load and the drain of the second thin film transistor load are made of conductor layers which are stacked on the semiconductor substrate with an insulator layer interposed between the conductor layers, and a top one of the stacked conductor layers makes contact with a top surface of a bottom one of the stacked conductor layers and with side surfaces of each conductor layer provided between the top and bottom conductor layers within the connecting region.

REFERENCES:
patent: 4764801 (1988-08-01), McLaughlin et al.
patent: 4931410 (1990-06-01), Tokunaga et al.
patent: 5028975 (1991-07-01), Nagasawa et al.
patent: 5034797 (1991-07-01), Yamanaka et al.
patent: 5210429 (1993-05-01), Adan
Yamanaka et al., "A 25 .mu.m.sup.2 New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity," International Electron Devices Meeting, Dec. 1988, San Francisco, Calif., pp. 48-51.
Ishibashi et al., "An .alpha.-Immune, 2-V Supply Voltage SRAM Using a Polysilicon PMOS Load Cell," IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, New York, N.Y., pp. 55-60.
Adan et al., "A Half-Micron SRAM Cell Using a Double-Gated Self-Aligned Polysilicon PMOS Thin Film Transistor (TFT) Load," Symposium on VLSI Technology, Jun. 1990, Honolulu, Japan, pp. 19-20.

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