Serial random access memory device capable of reducing peak curr

Details Serial random access memory device capable of reducing peak curr Serial random access memory device capable of reducing peak curr

1994-08-09

1996-05-28

Nelms, David C.

Static information storage and retrieval

Addressing

Multiple port access

365227, 36523003, 36523009, 365240, 36518912, G11C 800

Patent

active

055218776

ABSTRACT:
In a semiconductor memory device comprising a plurality of memory cells which are arranged on a cell area defined by a first number of column signal lines and a second number of row signal lines, a row decoder produces a row selection signal through one of the second number of row signal lines. A serial access section includes a data register and serially accesses a part of the plurality of memory cells arranged along the one end of the second number of row signal lines. The plurality of memory cells are divided into a plurality of cell blocks. The data register is divided into a plurality of subword data registers each of which corresponds to each of the plurality of cell blocks. The serial access section accesses the plurality of cell blocks, in order, at a predetermined interval. Each of the plurality of subword data registers stores subword data in each of the plurality of cell blocks, in order, at the predetermined interval.

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Syoji Ishimoto et al, "Special Application Memories", 1985 IEEE International Solid-State Circuits Conference, pp. 38 and 39, Feb. 13, 1985.

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