Method for forming a metal wiring layer in a semiconductor devic

Details Method for forming a metal wiring layer in a semiconductor devic Method for forming a metal wiring layer in a semiconductor devic

1992-06-11

1994-06-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437199, 437203, 437247, 437197, H01L 2144

Patent

active

053189230

ABSTRACT:
A method for forming a metal layer in a semiconductor device is disclosed. The method includes a first process for depositing a metal at an optional temperature after forming the pattern of a contact hole on the semiconductor substrate on which the stepped portion is formed, and a second process for annealing the deposited metal in a sputtering reaction chamber to fill up the contact hole with said metal. According to the invention, it is possible to completely fill up a contact hole having a high aspect ratio.

REFERENCES:
patent: 4970176 (1990-11-01), Tracy et al.
patent: 5071791 (1991-12-01), Inoue et al.
patent: 5147819 (1992-09-01), Yu et al.

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