Dynamic semiconductor memory device of a twisted bit line system

Details Dynamic semiconductor memory device of a twisted bit line system Dynamic semiconductor memory device of a twisted bit line system

1990-10-24

1992-02-11

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

365149, 365210, 365203, G11C 1140

Patent

active

050880640

ABSTRACT:
An arrangement for providing a compensation of capacitance coupling between word lines and bit lines in a memory structure including twisted bit lines. Two dummy word lines maintained at a predetermined potential are formed at a twisted portion of a pair of bit lines. Dummy cells are provided at respective twisted portions of the dummy word lines and the bit lines. A plurality of word lines are formed in a direction intersection with the bit lines and the word lines are divided into four word line groups according to positions of the twisted portions of the bit line pairs. When an arbitrary word line is selected, a potential of at last one dummy word line corresponding to the word line group to which the selected word line belongs is lowered. Consequently, the rise of the potential of the bit lines caused by the selection of the word line is compensated for by the lowering of the potential of at least one dummy word line, making it possible to decrease errors in reading. Particular cell layer arrangements simplify increase in integration density in the combination of dummy cell compensation with the twisted bit line balancing of capacitance coupling.

REFERENCES:
patent: 3942164 (1976-03-01), Dunn

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