Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1990-12-04

1992-09-01

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

36523001, G11C 1300

Patent

active

051445840

ABSTRACT:
A semiconductor memory device comprises a random memory cell array halved into first and second memory areas, and a data register coupled to digit lines of the random memory cell array in parallel for temporarily holding data read out onto the respective digit lines from selected memory cells. A row address generator receives an input row address and generates a first row address signal designating a first row corresponding to the input row address, and a second row address designating a second row different from the first row. A controller is coupled to first and second half portions of each of the word lines, and responds to the first and second row address signals so as to cause to transfer to the data register, data stored in the memory cells which are included in one row designated by the first row address signal and which belong to one of the first and second memory areas, and also so as to cause to refresh the memory cells which are included in one row designated by the second row address signal and which belong to the other of the first and second memory areas.

REFERENCES:
patent: 4855959 (1989-08-01), Kobayashi
patent: 4982369 (1991-01-01), Tatematsu

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