Electrostatic protection circuit for semiconductor chip

Electricity: electrical systems and devices – Safety and protection of systems and devices – Impedance insertion

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361100, H02H 900

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active

051445190

ABSTRACT:
A semiconductor chip protection circuit has a transmission gate TG.sub.11 disposed between an input pin 11 and an input terminal of an internal circuit 12, and two further transmission gates TG.sub.12, TG.sub.13 respectively connected between the input terminal of the internal circuit and a power terminal V.sub.DD, and between the input terminal and a ground terminal. Two additional transmission gates TG.sub.14, TG.sub.15 are connected respectively between an output terminal of the internal circuit and the power terminal, and between the output terminal and ground. At least one final transmission gate TG.sub.16 is connected between the power terminal and ground. Electrostatic charges are smoothly discharged because of the low resistance value of the N-type and P-type transistors of gates TG.sub.11 to TG.sub.16.

REFERENCES:
patent: 3947727 (1976-03-01), Stewart
patent: 4043112 (1977-08-01), Tanaka
patent: 4437135 (1984-03-01), Ogata et al.
patent: 4728932 (1988-03-01), Atherton
patent: 4930037 (1990-05-01), Woo
Microelectronics, Second Edition, Jacob Millman, Ph.D.; Arvin Grabel, Sc.D., pp. 238-240.

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