Output buffer circuit

Details Output buffer circuit Output buffer circuit

1998-03-27

1999-10-26

Santamauro, Jon

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 57, 326 86, H03K 19003

Patent

active

059735090

ABSTRACT:
An output buffer circuit for controlling operation of an input and output terminal utilizing a pair of MOS Transistors respectively formed in first and second wells in a substrate. The input and output terminal is connected commonly to the source of the first MOS transistor, to the drain of the second MOS transistor and to the well of the first MOS transistor in order to hold the well at the same potential as the input and output terminal. Also included is a first potential point applying a first potential to the drain of the first MOS transistor and a second potential apply commonly to the source and the well electrode of the second MOS transistor. The resulting structure controls the operating state of the input and output terminal in a manner which allows for an enhanced output potential.

REFERENCES:
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patent: 4506164 (1985-03-01), Higuchi
patent: 4591745 (1986-05-01), Shen
patent: 5124579 (1992-06-01), Naghshineh
patent: 5243236 (1993-09-01), McDaniel
patent: 5382846 (1995-01-01), Shigehara et al.
patent: 5422592 (1995-06-01), Asahina
patent: 5543733 (1996-08-01), Mattos et al.
patent: 5546020 (1996-08-01), Lee et al.
patent: 5635860 (1997-06-01), Westerwick
patent: 5650742 (1997-07-01), Hirano
patent: 5661414 (1997-08-01), Shigehara et al.

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