Semiconductor device with marginless contact hole

Details Semiconductor device with marginless contact hole Semiconductor device with marginless contact hole

1997-07-29

1999-10-26

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257369, 257381, H01L 2976

Patent

active

059733713

ABSTRACT:
A semiconductor device is provided, which is capable of miniaturization to a level corresponding to 1-Gb DRAMs. A first interlayer insulating layer is formed on or over a semiconductor substrate to cover a first-level conductive layer. First and second conductive sublayers of a second-level conductive layer are formed on the first interlayer insulating layer. First and second insulating caps are formed on the first and second sublayers, respectively. A lower contact hole penetrating the first insulating layer is formed to be self-aligned with the first and second sublayers. A conductive pad is formed on the first-level conductive layer in the lower contact hole to be electrically insulated from the first and second sublayers by an insulating spacer. A second interlayer insulating layer with an upper contact hole communicating with the lower contact hole is formed on the first interlayer insulating layer. A third-level conductive layer is formed on the second interlayer insulating layer to be contacted with the conductive pad through the upper contact hole.

REFERENCES:
patent: 5684313 (1997-11-01), Kenney
patent: 5705838 (1998-01-01), Jost et al.
patent: 5706164 (1998-01-01), Jeng
Yamada, et al., "Spread Source/Drain (SSD) MOSFET Using Selective Silicon Growth for 64Mbit DRAMs", IEDM Technical Digest, 1989, pp. 35-38.
Mizuno, et al. "Si.sub.3 N.sub.4 /SiO.sub.2 Spacer Induced High Reliability in LDDMOSFET and Its Simple Degradation Model", IEDM Technical Digest, 1988, pp.234-237.

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