Methods and arrangements for forming a tapered floating gate in

Details Methods and arrangements for forming a tapered floating gate in Methods and arrangements for forming a tapered floating gate in

1997-12-18

1999-10-26

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257317, 257508, H01L 29788

Patent

active

059733535

ABSTRACT:
Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates by advantageously tapering the sidewalls of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the suicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.

REFERENCES:
patent: 5021848 (1991-06-01), Chiu
patent: 5432112 (1995-07-01), Hong
patent: 5508957 (1996-04-01), Momodomi et al.
patent: 5830771 (1998-11-01), Fukatsu et al.

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