Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1995-04-13
1997-06-10
Picardat, Kevin
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
257723, 438108, H01L 2160
Patent
active
056375360
DESCRIPTION:
BRIEF SUMMARY
This is the U.S. national application of PCT/FR94/00986 filed on Aug. 5, 1994.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The subject of the present invention is a process for interconnecting semiconductor chips in three dimensions, as well as the electronic component resulting therefrom, each of the chips containing, for example, an electronic component, an integrated circuit, or a sensor, the whole being able to constitute for example a micromachine.
2. Discussion of Background
The construction of current electronic systems, both civil and military, must take into account ever greater demands of compactness, owing to the ever higher number of circuits employed.
With this in mind, it has already been proposed to construct stacks of so-called "three-dimensional" (3D) integrated circuits, as described for example in French Patent Application No. 2,670,323 in the name of Thomson-CSF. According to this construction, the semiconductor chips are stacked after having been provided with connection wires oriented towards the lateral faces of the stack, and then they are consolidated together by embedding, for example in a resin; the interconnections of the chips are then made on the faces of the stack.
SUMMARY OF THE INVENTION
The purpose of the present invention is to modify this process so as to allow the resulting 3D component to meet stricter specifications for harsh environments, in space for example. This is achieved, in particular, by avoiding the semiconductor chips being finally embedded in a resin, this allowing, on the one hand, better performance at high frequency and, on the other hand, a lessening of the mechanical stresses exerted on the chips during temperature variations.
More precisely, according to the process of the invention, wafers, each including one or more semiconductor chips, are provided with leads, wires for example, connected to the pads of the chips and oriented towards the lateral faces of the stack, then the chips are stacked and embedded in a material capable of being selectively removed subsequently; next, the faces of the stack are treated so as to reveal the cross-sections of the above leads, connections intended to interconnect the cross-sections of these leads electrically are formed on the faces of the stack, and then the embedding material is selectively removed.
BRIEF DESCRIPTION OF THE DRAWINGS
Other subjects, features and results of the invention will emerge from the following description given by way of example and illustrated by the appended drawings which represent:
FIG. 1, one embodiment of the method according to the invention;
FIG. 2a, an exploded perspective view of an embodiment of the first steps of the method according to the invention;
FIG. 2b, a partial sectional view of FIG. 2a;
FIGS. 3, 4, 5a and 5b, various embodiments of the first step of the method according to the invention;
FIG. 6, a sectional view of the stack obtained on the basis of one of the above embodiments;
FIG. 7, the stack obtained after slicing its faces;
FIGS. 8a and 8b, two variant embodiments of the stack obtained after removing the embedding material;
FIG. 8c, a variant of the above figure.
In these various figures, the same references relate to the same elements. Furthermore, for clarity, the drawings are not to true scale. Likewise, for simplicity described below is the case in which the stacked wafers each contain just a single semiconductor chip, but the invention is of course applicable to the case in which the wafers, or substrates, contain several chips.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 therefore illustrates one possible embodiment of the method according to the invention.
The first step, labelled 11, consists in electrically connecting leads to each of the pads of the semiconductor chips intended to make up the stack.
This step can be carried out in various ways.
A first embodiment is represented in FIGS. 2a and 2b, FIG. 2a being an exploded perspective view of several chips, for example two, and of their connection means, FIG. 2b being a sect
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Picardat Kevin
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