Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-09-25
1997-09-09
Beausoliel, Jr., Robert W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711129, 711138, 711154, 711160, G06F 1208, G06F 1100
Patent
active
056664826
ABSTRACT:
According to the present invention, faulty lines of data of a set associative cache memory containing one or more faulty data bits which are not repairable through conventional repair means such as row/column redundancy, are not updated following a cache miss condition and thereby effectively bypassed. Replacement logic circuitry detects and controls the state of a replacement status bit associated with each line of data of the set associative cache memory to determine if the line of data in the cache should be updated or bypassed. Thus, when replacing a line of data, the replacement logic circuitry detects the address of a faulty line of data in a particular set and avoids updating that faulty line of data in favor of updating another line of data of another set. The replacement logic circuitry may be used with a variety of replacement algorithms including the least recently used (LRU) replacement algorithm, the first in first out (FIFO) replacement algorithm, the last in first out (LIFO) replacement algorithm, the random replacement algorithm, or the pseudo LRU replacement algorithm.
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Fault-Tolerant Architecture in a Cache Memory Control LSI, Yasushi Ooi et al, 8107 IEEE Journal of Solid State Circuits, 27(1992) Apr., No. 4, New York, US.
Beausoliel, Jr. Robert W.
Galanthay Theodore E.
Jorgenson Lisa K.
Larson Renee M.
Palys Joseph E.
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