Level shifting circuit for suppressing output amplitude

Details Level shifting circuit for suppressing output amplitude Level shifting circuit for suppressing output amplitude

1992-12-10

1995-01-17

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326112, 326121, H03K 190175

Patent

active

053828461

ABSTRACT:
The source-drain paths of first and second N-channel MOS transistors are series-connected between a first node to which a first power source voltage is applied and a second node to which a ground voltage is applied. The gate of the first MOS transistor is supplied with an input signal and the gate of the second MOS transistor is supplied with a signal obtained by inverting the input signal by means of a CMOS inverter. The inverter is supplied with a second power source voltage which is independent from the first power source voltage as an operation power source voltage.

REFERENCES:
patent: 4704547 (1987-11-01), Kirsch
patent: 4730132 (1988-03-01), Watanabe et al.
patent: 4882534 (1989-11-01), Koshizuka
patent: 5057715 (1991-10-01), Larsen
patent: 5191244 (1993-03-01), Runaldue

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