Memory redundancy apparatus for single chip memories

Details Memory redundancy apparatus for single chip memories Memory redundancy apparatus for single chip memories

1980-09-30

1982-11-09

Stellar, George G.

Static information storage and retrieval

Read/write circuit

Bad bit

371 10, G11C 700

Patent

active

043588336

ABSTRACT:
An improved addressing means for single chip memories which include a plurality of redundant lines and associated cells is described. Y address signals are used during programming to select and program redundant X decoders. The redundancy apparatus is implemented without any additional package pins and programming may be performed after packaging. The apparatus includes means for permanently disabling all further programming of the redundancy circuitry to prevent inadvertent programming by a user.

REFERENCES:
patent: 4051354 (1977-09-01), Choate
patent: 4281398 (1981-07-01), McKenny et al.

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