Method for forming a self-aligned lateral DMOS transistor

Details Method for forming a self-aligned lateral DMOS transistor Method for forming a self-aligned lateral DMOS transistor

1993-07-01

1994-11-29

Fourson, George

Fishing, trapping, and vermin destroying

437 45, 437 44, 148DIG126, H01L 21265

Patent

active

053690451

ABSTRACT:
A method of forming a LDMOS transistor device 10 is disclosed herein. A semiconductor layer 14 is provided. The layer 14 may be an n-type RESURF region formed over a p-substrate 12. An insulating layer 24, such as a field oxide, is formed on the semiconductor layer 14. The insulating layer 24 is then patterned to expose source and drain windows. A D-well region 20 is then formed within the source window portion of the semiconductor layer. A sidewall region is formed adjacent a sidewall of the insulating layer around the source window. The source and drain regions 16 and 18 are then formed, for example by implanting arsenic or phosphorus ions. A gate electrode 26 is formed over a portion of the D-well region 20 between the source region 16 and the insulating layer 24. The gate electrode 26 is formed over a channel region within the D-well 20 between the source 16 and drain 18.

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