Fast static cascode logic gate

Details Fast static cascode logic gate Fast static cascode logic gate

1994-08-11

1995-08-01

Hudspeth, David R.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326 34, 326 86, H03K 19096

Patent

active

054382831

ABSTRACT:
A fast static logic gate contains a pullup logic network and a pulldown logic network configured to implement a logic function. The pullup logic network is coupled to receive gate inputs, and generates a first voltage level at a first node to represent a first state in accordance with the gate inputs and logic function. The first voltage level is less than the source voltage for the fast static logic gate circuit. A leaker circuit generates a second voltage level at the first node in response to a second state of the logic function. A driver circuit is coupled to a second node for generating an output. The pulldown logic network receives the gate inputs, and generates a second voltage level for the output to represent the second state in accordance to the gate inputs and logic function. The switch circuit couples the first node to the second node when the logic function generates the second state, and couples the source voltage to the second node when the logic function generates the first state. In this way, the driver circuit receives a full source voltage representing the first state.

REFERENCES:
patent: 4080539 (1978-03-01), Stewart
patent: 4360901 (1982-11-01), Proebsting
patent: 4404474 (1983-09-01), Dingwall
patent: 4491748 (1985-01-01), Chappell et al.
patent: 4498021 (1985-02-01), Uya
patent: 4645952 (1987-02-01), van Tran
patent: 5264741 (1993-11-01), Srinivasan et al.
patent: 5276366 (1994-01-01), Quigley et al.

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