Method of manufacturing a semiconductor integrated circuit devic

Details Method of manufacturing a semiconductor integrated circuit devic Method of manufacturing a semiconductor integrated circuit devic

1975-09-30

1977-06-21

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

148187, 156657, 156659, 357 36, H01L 750

Patent

active

040309541

ABSTRACT:
A method of manufacturing a semiconductor integrated circuit device including N-P-N transistors is characterized in that a base region of at least one of the N-P-N transistors is partially etched and removed with chemicals, thus to be formed with a depression, and that an emitter region opposite in the conductivity type to the base region is formed in the base region beneath the depression, whereby the at least one N-P-N transistor is made higher in the current gain h.sub.FE than the other N-P-N transistors being the main constituents of the integrated circuit device.

REFERENCES:
patent: 3808058 (1974-04-01), Henning
patent: 3891469 (1975-06-01), Moriyama et al.

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