Semiconductor memory device having capacitor of thin film transi

Details Semiconductor memory device having capacitor of thin film transi Semiconductor memory device having capacitor of thin film transi

1991-05-23

1994-01-25

Zazworsky, John

Static information storage and retrieval

Read/write circuit

307279, 365182, 365187, G11C 1140

Patent

active

052821625

ABSTRACT:
The gate of a transistor Q1 serving as a selection transistor is connected to a word line and the source thereof is connected to a bit line BL. The gate of a transistor Q2 serving as a cell capacitor is connected to the drain of the transistor Q1 and the drain thereof is connected to a pulse generation circuit. Whether an inverted layer is formed in the channel region of the transistor Q2 or not is determined according to the stored data. An inverted layer is formed in the channel region of the transistor Q2 having data "1" stored as storage data. The source of the transistor Q2 is connected to the gate of a transistor Q3. The drain of the transistor Q3 is connected to a pulse generation circuit 11 and the source thereof is connected to the drain of the transistor Q1. The transistor Q2 having an inverted layer formed therein is turned on when a preset voltage is supplied from the pulse generation circuit 11 in the stored data reading operation, and in this case, the transistor Q3 is turned on. Therefore, a current can be supplied to the bit line BL from the pulse generation circuit 11 via the transistor Q3 and the selected transistor Q1.

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M. Aoki et al., IEEE Journal of Solid State Circuits, vol. 24, No. 5, Oct. 1989, "A 1.5-V DRAM for Battery-Based Applications."

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