Self aligned method for differential oxidation rate at shallow t

Details Self aligned method for differential oxidation rate at shallow t Self aligned method for differential oxidation rate at shallow t

1998-02-23

2000-03-21

Guay, John

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257397, 257409, H01L 2702, H01L 2968

Patent

active

060406070

ABSTRACT:
A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate is provided. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure, preferably through the use of an ion implantation into a tilted or inclined substrate. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the proximal portions relative to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, a first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate. The increased oxide thickness adjacent to the discontinuities of the isolation trench reduces the electric field across the oxide.

REFERENCES:
patent: 5146291 (1992-09-01), Watabe et al.
patent: 5391907 (1995-02-01), Jang
patent: 5494846 (1996-02-01), Yamazaki
patent: 5869858 (1999-02-01), Ozawa et al.
Wolf et al., Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, 1986, p. 183.

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