Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-01-26

2000-03-21

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257 66, 257314, 257368, 257390, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

060406054

ABSTRACT:
A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

REFERENCES:
patent: 5411905 (1995-05-01), Acovic et al.
patent: 5412600 (1995-05-01), Nakajima
patent: 5576570 (1996-11-01), Ohsawa et al.
patent: 5654577 (1997-08-01), Nakamura et al.
patent: 5793087 (1998-08-01), Chevallier
Yano et al., "Room-Temperature Single-Electron Memory", IEEE Transactions on Electron Devices, vol. 41, No. 9, Sep. 1994.

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