Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1996-05-23

1998-01-20

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

365193, G11C 700, G11C 2900

Patent

active

057107378

ABSTRACT:
A sense amplifier (2) is connected to an input/output circuit (7), transmitting input/output data therebetween. The input/output circuit (7) is connected to an address scramble circuit (8). Furthermore, the input/output circuit (7) is connected to a data input/output terminal (DIO), externally transmitting data. The address scramble circuit (8) receives input data (INTDQ) from the data input/output terminal (DIO) and converts the input data (INTDQ) into write data (WD) in accordance with the layout of memory cells in a memory array (1) in response to a burn-in mode signal (BIT) outputted from an address key circuit (9) and a row address first signal RAF outputted from a row address buffer (6). Having the above configuration, a semiconductor memory device can be provided, which permits a prescribed stress to be imposed on its internal circuit only by inputting simple data even in a burn-in test. Moreover, a semiconductor memory device can be provided, which allows an external verification as to whether the device itself enters a burn-in mode or not.

REFERENCES:
patent: 5381373 (1995-01-01), Ohsawa
patent: 5471429 (1995-11-01), Lee et al.

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