Semiconductor device having contact between wiring layer and imp

Details Semiconductor device having contact between wiring layer and imp Semiconductor device having contact between wiring layer and imp

1992-06-15

1994-01-25

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257385, 257756, H01L 2348, H01L 2946, H01L 2954

Patent

active

052818381

ABSTRACT:
A semiconductor device is disclosed that can form contacts with ease even if the distance between adjacent gate electrodes is reduced in accordance with larger scale integration of semiconductor devices. The semiconductor device includes a polysilicon pad 8c connected to impurity implanted layers 5a and 7a, formed over sidewalls 6a and 6b of gate electrodes 3a and 3b and insulating films 4a and 4b; and a polysilicon pad 11a connected to impurity implanted layers 5b and 7b, formed over polysilicon pad 8c with an insulating film 9 and sidewalls 10b therebetween. Even if elements are miniaturized to have reduced gate electrode length and gate electrode distance in accordance with larger scale integration of a semiconductor device, polysilicon pads 8c and 11a can be formed with ease between impurity implanted layers 5a, 7a and an upper layer wiring 13a, and between impurity implanted layers 5b, 7b and an upper layer wiring 13b, respectively. Thus, contact holes 15a and 15b can be formed without difficulty for forming upper layer wirings 13a and 13b, even if semiconductor devices are increased to larger scale integration.

REFERENCES:
patent: 4234889 (1980-11-01), Raymond, Jr. et al.
patent: 4803534 (1989-02-01), Koike et al.
patent: 5012310 (1991-04-01), Kimura et al.
patent: 5101251 (1992-03-01), Wakamiya et al.
Konaka et al., "A 20-ps Si Bipolar IC Using Advanced Superself-Aligned Process Technology with Collector Ion Implantation", IEEE Transactions on Electron Devices, vol. 36, No. 7, Jul., 1989, pp. 1370-1375.

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