Jitter/wander reduction circuit for pulse-stuffed, synchronized

Details Jitter/wander reduction circuit for pulse-stuffed, synchronized Jitter/wander reduction circuit for pulse-stuffed, synchronized

1994-07-27

1996-07-23

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375363, 370102, H04L 700

Patent

active

055397859

ABSTRACT:
A jitter/wander reduction circuit is provided for a desynchronizer deriving an output clock signal from an independent clock signal and phase adjustment signals. Phase adjustment signals relate to a deviation of the independent clock signal from an input clock signal. The circuit includes a frequency offset estimation circuit receiving phase adjustment signals and providing a frequency offset estimation signal. A phase controller receives the frequency offset estimation signal, provides a feedback signal to the frequency offset estimation circuit, and provides a phase difference signal. A clock generator circuit receives the independent clock signal and the phase difference signal. The independent clock signal is adjusted based on the phase difference signal to provide an output clock signal.

REFERENCES:
patent: 3812430 (1974-05-01), Schmidt et al.
patent: 4731646 (1988-03-01), Kliem
patent: 4792966 (1988-12-01), Ballweg
patent: 4847875 (1989-07-01), Choi
patent: 5235531 (1993-08-01), Foerg
patent: 5313502 (1994-05-01), Nawrocki et al.

Affiliated with

Also associated with

Rating

Jitter/wander reduction circuit for pulse-stuffed, synchronized does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Jitter/wander reduction circuit for pulse-stuffed, synchronized , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Jitter/wander reduction circuit for pulse-stuffed, synchronized will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-719860