Packet processing method and apparatus

Details Packet processing method and apparatus Packet processing method and apparatus

1991-10-04

1995-03-14

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

3701101, H04J 324

Patent

active

053982452

ABSTRACT:
A method and apparatus for processing a data packet, for delivery to a designated location, store selective portions of the packet header in a high speed cache memory to increase processing speed and hence throughput for a packet delivery system. The apparatus and method receive the packets from a data channel source and store portions of the header in cache, and at least the remainder of each data packet is stored in a slower speed memory. A CPU accesses the stored header portion of each packet in cache for necessary protocol and destination information processing of the data packet. The header portions are then overwritten with new data and combined with the remainder of the data packet stored in slower speed memory for transmission to the next packet destination. Preferably, the address at which the remainder portions are stored in slower speed memory determine the cache addresses at which the header portion is stored in high speed cache memory.

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patent: 5062106 (1991-10-01), Yamazaki et al.
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patent: 5140582 (1992-08-01), Tsuboi et al.
patent: 5140583 (1992-08-01), May et al.

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