Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1980-06-02
1983-10-25
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Data refresh
365195, 365200, G11C 700
Patent
active
044123140
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention pertains to integrated, semiconductor memories and in particular to such a memory adapted for use in conjunction with an error detecting and correcting circuit.
BACKGROUND ART
High density, semiconductor memories have become extensively used in computer systems as the cost of such memories has dropped. Semiconductor memories have largely replaced previously used magnetic core type memories. However, semiconductor memories are prone to single bit errors as a result of alpha particle radiation. When an alpha particle strikes the semiconductor material, electron-hole pairs are generated which can produce leakage currents that can discharge a node and change a data state. The electron-hole pairs can cause memory storage capacitors to be discharged. The bit lines in a dynamic memory are also susceptible to alpha particles. In all cases the alpha particles cause a loss of data even though no permanent damage is done to the circuit. The alpha particles are primarily derived from radioactive impurities used in the packaging of the semiconductor chip. Single bit errors such as caused by alpha particles are referred to soft errors and occur rather infrequently.
The semiconductor memories in computer systems are becoming quite large and in many cases data must be stored in the memories for an appreciable period of time, days, weeks and even longer. As the memories become larger and the storage time becomes longer, the probability of incurring soft errors due to alpha particle radiation increases. In many applications the accuracy of the data stored in the semiconductor memory is critical and the loss of a single bit within a field of data can produce a serious problem in the application being conducted by the computer.
There are techniques such as Hamming codes which can be used to detect errors but generally to detect only one error per data word. Since alpha errors occur intermittently there can occur two errors in the same word if the data pattern is corrected only when it is read out. Most existing systems generally perform error correction only when the data word is read out. Therefore it is possible that two errors can accumulate and the data word is lost.
Therefore, there exists a need for a semiconductor memory circuit and a memory system for detecting the occurrence of soft errors such as caused by alpha particles and correcting these errors on a recurring basis to prevent the accumulation of more errors in the data pattern stored in the semiconductor memory than can be handled by an error correction system.
DISCLOSURE OF THE INVENTION
The present invention is a dynamic, integrated, semiconductor memory circuit wherein a memory cell is accessed through row and column lines at a given memory address. The memory address is stored in an address buffer. The memory cell is accessed in response to the memory address and in response to a row address strobe (RAS) signal and a column address strobe (CAS) signal. The RAS signal generates row clock signals which access and refresh the memory cells on the row corresponding to the memory address in the address buffer. The CAS signal generates column clock signals for connecting the addressed memory cell to a data bus. The circuit of the present invention includes a terminal for receiving a refresh signal. Within the memory circuit row clock signals are generated upon receipt of the refresh signal as with receipt of the RAS signal. Logic circuitry is provided for inhibiting the generation of the column clock signals and/or the input/output circuitry in the absence of the RAS signal. The circuit further provides for transferring an externally supplied memory address to an address buffer when either the RAS signal or the refresh signal has been received at the circuit.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic illust
REFERENCES:
patent: 3719932 (1973-03-01), Cappon
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4112514 (1978-09-01), Spoelder
patent: 4183096 (1980-01-01), Cenker et al.
Harroun, "Storage Refresh Control and Synchronization", IBM Tech. Disc. Bul., vol. 15, No. 1, 6/72, pp. 257-258.
Aichelmann et al., "Memory Initialization by Deferred Refresh", IBM Tech. Disc. Bul., vol. 18, No. 5, 10/75, p. 1457.
Hecker Stuart N.
Mostek Corporation
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