Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Patent
1994-04-11
1996-07-23
Callahan, Timothy P.
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
327156, 327159, 327161, 327292, H03L 700
Patent
active
055393446
ABSTRACT:
The objects are to speed up the operation of an integrated circuit device having a sequential circuit and increase margin of phase synchronization for performing data processing of time sequential circuit. The phase-locked circuit (57) is provided in the integrated circuit (50), and the clock signal (CK7) which is inputted from the outside through the phase-locked circuit is supplied to the sequential circuit (52). The data outputted from the sequential circuit (52) is fed back from the output end of the buffer (Bu56) to the phase-locked circuit (57). In the phase-locked circuit (57), the clock signal (CK7) inputted through the buffer (Bu50) and the output data of the sequential circuit (52) are compared in phase and the phase of the clock signal outputted to the sequential circuit (52) is adjusted so that the phases thereof agree. The output data (DO7) outputted from the sequential circuit (52) is not delayed with respect clock signal (CK7). Accordingly, the data processing in the integrated circuit (70) can be speeded up.
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IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1218-1223, Mark G. Johnson, et al., "A Variable Delay Line PLL For CPU-Coprocessor Synchronization".
Callahan Timothy P.
Lam T.
Mitsubishi Denki & Kabushiki Kaisha
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