Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1993-07-08
1995-03-14
Westin, Edward P.
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 93, 326 21, 327292, H03K 19096, H03K 512, H03K 19177
Patent
active
053979435
ABSTRACT:
There is disclosed herein a method and apparatus for distributing high speed clock signals on an integrated circuit while eliminating clock skew. The invention is particularly useful in field programmable gate arrays where the signal paths are defined by the user after the integrated circuit leaves the place of manufacture and enables field programmable gate arrays to operate at clock speeds in excess of 200 MHz, a speed not previously attainable. Clock skew is eliminated by generating differential clock signals at each of four corners of the array from master differential clock signal delivered simultaneously to each of the four corners. The differential clock signals generated at each corner have ramps the rise time of which slightly exceeds the propagation delay of a clock signal traversing the array. The true signal is propagated across both the top and bottom of the array of cells in the same direction and the complement clock signal is propagated across both the top and bottom of the array of cells in the opposite direction. At the top and bottom of each column, secondary clock receivers receive the true and complement clock signals and generate new differential column clock signals with ramps that are triggered at the time at each column when the true and complement clock signals "crossover", i.e., are equal in amplitude. The ramps of these column clock signals also have rise times which slightly exceed the propagation delay of a clock signal propagating down a column. The differential clock signals are generated at the top and bottom of each column. The true clock signal generated at the top of each column is propagated down each column and the complement clock signal generated at the bottom of each column is propagated up the column. Each cell uses as its clock marker the crossover point between the counter-propagating true and complement clock signals.
REFERENCES:
patent: 4812684 (1989-03-01), Yamagiwa et al.
patent: 5045725 (1991-09-01), Sasaki et al.
patent: 5066877 (1991-11-01), Hamano et al.
patent: 5172330 (1992-12-01), Watanabe et al.
Vora Madhukar B.
West Burnell G.
Driscoll Benjamin D.
Dyna Logic Corporation
Fish Ron
Westin Edward P.
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