Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-07-01
1999-09-28
Sheikh, Ayaz R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395293, 395726, 711141, G06F 1300
Patent
active
059601795
ABSTRACT:
In a networked computer system that includes an omnibus system coupled to a plurality of workstation/computer subsystems, an optimal global reordering of transactions seeking Address Bus access is provided. Access requests are asserted by devices associated with circuit cards, each such card including an address controller, memory, and a coherent input queue. Transactions occurring on the omnibus are loaded into the associated address controller coherent input queue. A global network interface is coupled to the omnibus system and may assert an IGNORE signal, amd includes a table storing all cache lines in the distributed memory system. A transaction seeking to access an address holding invalid data or a remote address is detected by the global network interface, which asserts the IGNORE signal, thus blocking the transaction from loading into the coherent input queue. At a later time when the subject address retains valid data, the interface reissues an identical transaction on the bus. In this fashion, an optimal global reordering of transactions is executed in a manner making the order of transactions observed on all the buses compatible with each other.
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Kaufman Michael A.
Sheikh Ayaz R.
Sun Microsystems Inc.
Thlang Eric S.
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