Scheduler design for ATM switches, and its implementation in a d

Details Scheduler design for ATM switches, and its implementation in a d Scheduler design for ATM switches, and its implementation in a d

1996-09-13

1999-09-28

Ton, Dang

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370416, H04J 300

Patent

active

059599936

ABSTRACT:
A cell scheduler for a distributed shared memory switch architecture including a controller for scheduling transmissions of cells from output queues of the switch structure pursuant to one of several different scheduling modes. The controller receives a mode selection input, segregates the output queues into groups, assigns priority rankings to the groups, and applies one of scheduling disciplines at each group of output queues as determined by the mode selection input and the priority rankings. The groups of output queues include a group of per-Virtual Channel (VC) queues and at least one group of First In-First Out (FIFO) queues. The scheduling disciplines include a Weighted Fair Queuing (WFQ) scheduling discipline applied by the controller at the group of per-VC queues and a Round Robin (RR) scheduling discipline applied by the controller at the at least one group of FIFO queues. The priority rankings comprising a highest priority ranking which is assigned to the group of per-VC queues.

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