Increasing testability by clock transformation

Details Increasing testability by clock transformation Increasing testability by clock transformation

1996-04-24

1997-04-29

Canney, Vincent P.

Excavating

371 251, G06T 1100

Patent

active

056256302

ABSTRACT:
A method of increasing the testability of sequential circuit designs with use of a clock transformation technique. Circuit states which are difficult to reach, but are nonetheless required to detect at least one fault of the circuit, are automatically identified. In accordance with one illustrative embodiment, estimations of joint line probabilities are compared with a preselected threshold value to identify hard-to-reach states. Then, commonly clocked flip-flops which must be simultaneously assigned values in order to reach the identified states are partitioned into independently clocked groups of flip-flops. In this manner, hard-to-reach circuit states are transformed into easy-to-reach states, which, in turn, results in transforming difficult-to-detect faults into easy-to-detect faults.

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