Static information storage and retrieval – Read/write circuit – Signals
Patent
1995-06-07
1997-04-29
Yoo, Do Hyun
Static information storage and retrieval
Read/write circuit
Signals
365207, 36523006, 365233, G11C 700, G11C 800
Patent
active
056255950
ABSTRACT:
An improved DRAM is disclosed, in which a number of sense amplifiers to be activated simultaneously can be selected by using a bonding option method. An output signal /.o slashed..sub.A supplied from a bonding option circuit 11 is applied to column interlock releasing circuit 7. When an operation mode in which the number of the sense amplifiers to be activated simultaneously is large is selected, a column interlock releasing signal /.o slashed. is delayed, and enabling of a column decoder 3 is delayed. In the operation mode, in which the number of the sense amplifiers to be activated simultaneously is large, the enabling of the column decoder 3 is delayed, and a conducting timing of an IO gate circuit 16 is delayed. A sense amplifier 15 can sufficiently amplify a potential difference between bit lines, so that an error in the data reading operation is prevented.
REFERENCES:
patent: 4996671 (1991-02-01), Suzuki et al.
patent: 5053997 (1991-10-01), Miyamato
patent: 5065365 (1991-11-01), Hirayama
patent: 5132932 (1992-07-01), Tobita
Mitsubishi Denki & Kabushiki Kaisha
Yoo Do Hyun
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