Electrically programmable memory cell arrangement and method for

Details Electrically programmable memory cell arrangement and method for Electrically programmable memory cell arrangement and method for

1997-01-07

1999-09-28

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257316, H01L 2976

Patent

active

059593288

ABSTRACT:
An electrically programmable memory cell arrangement has a plurality of individual memory cells that respectively has an MOS transistor with a gate dielectric with traps, and which are arranged in rows that run in parallel. Adjacent rows thereby respectively run in alternating fashion on the bottom of the longitudinal trenches (5) and between adjacent longitudinal trenches (5) and are insulated against one another. The memory cell arrangement can be manufactured by means of self-adjusting process steps with a surface requirement per memory cell of 2 F.sup.2 (F: minimum structural size).

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