Semiconductor memory cell having a trench structure

Details Semiconductor memory cell having a trench structure Semiconductor memory cell having a trench structure

1992-10-05

1994-02-08

Ngo, Ngan

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257329, 257330, 257331, 257334, 257374, 257393, 257401, 257903, H01L 2910, H01L 2978, H01L 2702

Patent

active

052850935

ABSTRACT:
In one embodiment, a semiconductor memory cell (10) having a trench (24) and access transistor (54) formed in a well region (20). The trench (24) substantially contains an inverter (60) which is electrically coupled to ground and power signals by buried layers (12, 18) in the substrate (11). The inverter (60) has a toroidal, shared-gate electrode (40) which electrically controls a driver transistor (32) in the wall (26) of the trench (24), and a thin-film load transistor (42) in the central portion of the trench (24). A portion of the toroidal, shared gate electrode extends to an adjacent well region (20') and contacts well region (20') at cell node (13'). A ground signal is provided to load transistor (42) at the bottom surface (28) of the trench (42). A supply signal is provided by a buried layer (18) which is integral with driver transistor (32).

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Eklund, et al.; "A 0.5 .mu.m BiCMOS Technology for Logic and 4 Mbit-Class SRAM's"; IEDM; pp. 425-428 (1989).

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