Digital phase-lock loop control system

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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Details

375371, 375374, 375375, 331 18, 331 25, H03D375376

Patent

active

058320482

ABSTRACT:
A phase-locked loop implemented in all-digital components uses a stochastic approach to detect errors in phase position and relative velocity. Using a history circuit and an adjustment-intensity selection circuit appropriate corrections in phase and frequency are made. The history circuit keeps a running record of a series of binary results (0 or 1) as received from a phase comparator. History components collected include the number of consecutive oscillator periods in which the phase offset (0 or 1) has remained the same and the number of oscillator periods in which the phase offset count has not exceeded 1.

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