Semiconductor processing method of forming electrically conducti

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

438618, H01L 2144

Patent

active

056656440

ABSTRACT:
A semiconductor processing method of forming an electrically conductive interconnect line having an electrical conductive covering predominately coextensive therewith, includes, a) providing an conductive interconnect line over a first electrically insulating material, the line having a top and sidewalls; b) selectively depositing a second electrically insulating material layer over the interconnect line and the first insulating material in a manner which deposits a greater thickness of the second insulating material atop the interconnect line than a thickness of the second insulating material over the first insulating material; c) anisotropically etching the second insulating material layer inwardly to at least the first insulating material yet leaving second insulating material over the top and the sidewalls of the interconnect line; and d) providing an electrically conductive layer over the anisotropically etched second insulating layer to form a conductive layer which is predominately coextensive with the interconnect line over the etched second insulating material. The method further comprises provision of a base electrically conductive layer beneath the first insulating material, with the anisotropically etching step etching through the first insulating material to the base conductive layer, and the conductive layer being provided in electrical connection with the base conductive layer. Integrated circuitry produced by the method and other methods is also disclosed.

REFERENCES:
patent: 4872947 (1989-10-01), Wang et al.
patent: 4877483 (1989-10-01), Bergemont et al.
patent: 4892753 (1990-01-01), Wang et al.
patent: 4892844 (1990-01-01), Cheung et al.
patent: 4894351 (1990-01-01), Batty
patent: 4997790 (1991-03-01), Woo et al.
patent: 5271972 (1993-12-01), Kwok
patent: 5378646 (1995-01-01), Huang et al.
patent: 5432128 (1995-07-01), Tsu
patent: 5473184 (1995-12-01), Murai et al.
patent: 5498571 (1996-03-01), Mori et al.
patent: 5508233 (1996-04-01), Yoset et al.
patent: 5536681 (1996-07-01), Jang et al.
Korczynski, E.J. et al., "Improved Sub-Micron Inter-Metal Dielectric Gap-Filing Using TEOS/Ozone APCVD", Microelectronics Manufacturing Technology, Jan. 1992, pp. 22-27.
Thomas Michael E. et al., "VLSI Multilevel Micro-Coaxial Interconnects For High Speed Devices", IEEE, 1990, pp. 55-58.
Fujino, K., "Silicon Dioxide Deposition By Atmospheric Pressure And Low-Temperature DVD Using TEOS and Ozone", J. Electrochem. Soc., vol. 137, No. 9, Sep. 1990, pp. 2884-2887.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor processing method of forming electrically conducti does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor processing method of forming electrically conducti, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor processing method of forming electrically conducti will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-69565

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.