Process of making a semiconductor device with a multilayer wirin

Details Process of making a semiconductor device with a multilayer wirin Process of making a semiconductor device with a multilayer wirin

1995-05-18

1997-09-09

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438648, 438649, 438669, 438625, H01L 2144, H01L 2148

Patent

active

056656424

ABSTRACT:
A method of manufacturing semiconductor interconnection includes the steps of providing a bottom conductive layer having an auxiliary conductive layer applied on top of the bottom conductive layer. The auxiliary conductive layer is patterned and subsequently a further conductive layer is applied over the patterned auxiliary conductive layer. A mask is then applied over the further conductive layer to form a pillar connection which provides a reliable connection in a semiconductor device.

REFERENCES:
patent: 3865624 (1975-02-01), Wilde
patent: 4087314 (1978-05-01), George et al.
patent: 4410622 (1983-10-01), Dalal et al.
patent: 4536951 (1985-08-01), Rhodes et al.
patent: 4614021 (1986-09-01), Hulseweh
patent: 4670091 (1987-06-01), Thomas et al.
patent: 4876176 (1989-10-01), Calviello et al.
patent: 4917759 (1990-04-01), Fisher et al.
patent: 4954423 (1990-09-01), McMann et al.
patent: 4966864 (1990-10-01), Pfiester
patent: 5037772 (1991-08-01), McDonald
patent: 5122477 (1992-06-01), Wolters et al.
patent: 5132775 (1992-07-01), Brighton et al.
patent: 5171713 (1992-12-01), Matthews
patent: 5175127 (1992-12-01), Manning
patent: 5187121 (1993-02-01), Cote et al.
patent: 5204285 (1993-04-01), Kakiuchi
patent: 5246876 (1993-09-01), Manning
patent: 5385867 (1995-01-01), Ueda et al.
patent: 5436199 (1995-07-01), Brighton
patent: 5470788 (1995-11-01), Biery et al.
patent: 5496771 (1996-03-01), Cronin et al.
Wolf et al., Silicon Processing for the VLSI Era, vol. I, Lattice Press, 1986, pp. 439-441.
Oakley et al., "Pillars--The Way to Two Micro Pitch Multilevel Metallization" IEEE, V-MIC Conf., Jun. 21-22, 1984, pp. 23-29.
Kitcher, "Integral Stud for Mutilevel Metal", IBM Tech Disclosure Bulletin, vol. 23, No. 4, Sep. 1980, p. 1395.

Affiliated with

Also associated with

Rating

Process of making a semiconductor device with a multilayer wirin does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process of making a semiconductor device with a multilayer wirin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process of making a semiconductor device with a multilayer wirin will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-69556